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Sequential Logic; “Use the appropriate symbol for each flip-flop used. (You do NOT need to show the circuit diagram within the flip-flops). This applies to all circuit diagrams in this assignment. Identify ONE change of state in the asynchronous counter that creates a timing problem on the output and identify the resulting instantaneous erroneous outputs
1. Design a sequential system to continuously output your set of eight different digits (01275438) in binary at the rate of one digit per clock pulse. In this design, for the next state logic sub-system, you should use a 3-bit asynchronous counter with the clock as the data input. Obtain any other necessary logic functions in their minimal 1st Canonical AND/OR/NOT form, and obtain their Boolean equations. Draw a gate-level circuit diagram of your system.
2. Redesign your system in question 1 using
i) An eight-state next-state logic system designed using synchronous trigger flip-flops where the state sequence is in ascending pure binary code, and an appropriate output logic encoder is used.
Redesign your system in question 1 using
ii) A next-state logic system designed using synchronous trigger flip-flops where the state sequence is your set of numbers and NO OUTPUT LOGIC is required.
NOTE. No external input is required in either of these designs.
Present minimal 1st canonical form AND/OR/NOT Boolean equations of any combinational logic used and give circuit diagrams of your systems.
Compare and contrast your designs in questions 1 and 2 in terms of amount of hardware required and ease of design. Comment on any likelihood (on not) of timing problems with Question 2 designs.
3. Take your original student number including any repeated digits (1202754) and design a sequential system to continuously output your number at the rate of one digit per clock pulse. If your number does NOT contain any repeated digit, change one digit so that there is at least one repeated digit in your sequence. Your next state subsystem should be a SEVEN-state machine based on JK flip-flops. The driving functions and any other necessary logic should be in minimal 2nd Canonical AND/OR/NOT form, and presented as Boolean equations.
Draw a detailed logic diagram of your system.
How would you modify your system so that the sequence stops at the end of your number, after having output all the digits once? Identify any changes to the flip-flop driving functions needed to achieve this.
4. Design a sequential system that has an input variable I. When I=1 the system should output continuously your original seven digit student number in binary. If however I is set to 0 at any time your system must output your number in reverse order, starting at the digit reached at the instant I was set to 0. Subsequent changes to input I must cause the digits to be output in forward order (I=1) or reverse order (I=0). On reaching the end of the number with I=1, start outputting the number again from the first digit. On reaching the beginning of the number with I=0 start outputting the number again from the last digit.
Use Data/delay flip-flops in your design and obtain any necessary combinational logic in its minimal NAND form, giving the appropriate Boolean equations.
Draw a detailed logic diagram of your system.
5. Delete the two most significant digits of your student number leaving a 5-digit number (02754). From this number obtain a 5-bit binary number by replacing the odd digits by 1 and the even digits by 0, assuming zero is even. (00110). If your five-bit number is all 0’s or all 1’s, contact me for a more suitable number.
You are now required to design a sequence detector which will indicate each time your 5-bit number has occurred in a stream of random bit-serial data. The detection of your number is indicated by setting an output variable, Z, to 1.
Obtain a State Transition Diagram for your system and from this diagram determine the sequence of state transitions for a random stream of 20 bits of data of your choice, which includes at least one occurrence of your five bit number (00110).
Obtain the Present/ Next State table of your system and if possible, state minimise the system.
Design the system using Delay/d
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